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LDPC Encoder/Decoder IP Core


Low-density parity check (LDPC) technology provides the high level of error correction needed for today’s low cost and high density flash memories. Symbyon’s patented solution is the most area and energy efficient LDPC implementation. It has support for soft data that estimates how likely each bit is correct. This information can greatly extend the useful life of a flash chip. This IP is fully configurable with support for multiple codeword rates and lengths using the same implementation.

Customizable parameters include codeword rate and length, parallelization, number of soft bits read from the flash memory and utilized by the LDPC detector. The Symbyon LDPC Encoder/Decoder IP core is delivered in Verilog RTL, which can be implemented in an ASIC or FPGA. It is fully tested and verified on FPGA and in software.

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