www.design-reuse-embedded.com
FortifyIQ, Inc.
Corporate Headquarters
FortifyIQ, Inc.
Newton
02458,
United States

FortifyIQ, Inc. SoC Catalog

About FortifyIQ, Inc.

FortifyIQ offers a new generation of products, protected against SCA and FIA, which utilize purely algorithmic, implementation-agnostic algorithms. It includes two families of products:

  • FortiCrypt – AES protected against SCA and FIA, including SIFA
  • FortiMac – HMAC SHA2 protected against SCA and FIA, including SIFA

Both families are unique in the market. Besides HW IP cores, SW libraries are offered in both families. These SW libraries provide the same purely algorithmic protections. FortiCrypt’s exceptional performance enables encryption/decryption of HD video streams on low-end CPUs, and it can be used even for devices already in the field which have no or insufficient protection.

FortiCrypt

All the FortiCrypt products (including the FortiCrypt SW library) are based on RAMBAM - the next-generation purely algorithmic, implementation-agnostic protection scheme of AES. They are designed to provide the highest level of protection against side-channel attacks (SCA) and fault injection attacks (FIA) including SIFA. Uniquely in the market, this is done without compromising high performance, low latency, and low gate count.

The RAMBAM protection scheme utilizes masking methods based on finite field arithmetic that implement attack resistance without incurring extra latency costs. The core protection mechanism was verified using the rigorous Test Vector Leakage Assessment (TVLA) test at 1B traces, both by FortifyIQ and by a third-party Common Criteria lab. Resistance to attacks was validated analytically and on a physical device. The cores are fully synthesizable and do not require custom cells or special place & route handling.

The AES cores are highly configurable providing a solution for various market segments from resource-constrained to performance-hungry. The configurable security parameter allows for achieving the user’s desired balance between gate count, latency, performance, and protection level. The user can choose a stand-alone cryptographic core or one integrated with a register block attached to one of the AMBA, AXI, or APB buses.

FortiCrypt IP cores are available in various configurations:

  1. ultra-low latency
  2. ultra-high performance
  3. ultra-low gate count
  4. a balanced solution that combines high security, high performance, low gate count, and low power consumption
  5. SW library that allows integrating built-in side-channel and fault injection attack protection even into your existing System-on-Chip

The balanced solution has a gate count comparable to unprotected solutions and the same latency and performance as unprotected solutions have, thereby upholding the original AES design goals of high performance, and low latency and gate count.

The FortiCrypt SW library provides the highest DPA resistance level while preserving exceptional performance enabling encryption/decryption of HD video streams on low-end CPUs.

FortiMac

All the FortiMac products, including the SW library, provide purely algorithmic and implementation-agnostic protection of HMAC SHA2 against side-channel attacks (SCA) and fault injection attacks (FIA) including SIFA. The protection is based on the threshold implementation approach. Resistance to attacks was validated analytically and on a physical device.
 Back

Partner with us

List your Products

Suppliers, list and add your products for free.

More about D&R Privacy Policy

© 2024 Design And Reuse

All Rights Reserved.

No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse.