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43 "Security IP" SoCs

1
Active mesh against tampering attacks - Active Shield
Attacks against digital circuits can be performed by directly tampering with the device s internal structure. These attacks are intrusive, and regroup attempts to directly probe or force signals, remo...

2
AES Key Wrap Engine
The EIP-37 is the IP for accelerating the AES Key Wrap cipher algorithm (NIST-Key-Wrap & RFC3394). Designed for fast integration, low gate count and full transforms, the EP-37 accelerator provides a r...

3
Anti Row-Hammer / Memory Attacks
The Anti Row-Hammer IP takes part in Memory Controller in order to protect the Memory against Rowhammer Attacks, especially on RAM. This IP is able to determine if the number of access requests to a M...

4
Basic AES Engine
The EIP-32 AES Engines implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publication 197. The accelerators include I/O register...

5
Boot Protection Pack / Root-of-Trust
The Boot Protection Pack is a solution provided by Secure-IC to ensure a Secure Boot function. The Boot Protection Pack provides a secure root-of-trust with a high level of resistance against malevole...

6
Camogates: protects against reverse-engineering
The Secure-IC s CamoGate IP has for goal to protect a circuit against reverse-engineering. Reverse engineering of an Integrated Circuit is a process which aims at identifying its structure, design and...

7
Circuit Camouflage Technology
Inside Secure Circuit Camouflage Technology, also known as SecureMedia Library (SML), is an anti-reverse engineering and anti-cloning protection for integrated circuits that has both Commercial and Government Applications.

8
CryptoCell-300 - Platform Security Solution for Devices with Strict Power and Area Constraints
The Arm CryptoCell-300 family of embedded security solutions serves high-efficiency systems with a small footprint and low power consumption.

9
DES/3DES engine
As part of Rambus award-winning silicon Intellectual Property (IP) product portfolio, the EIP-16 DES/3DES Engines implement the DES and 3DES algorithm, as specified in Federal Information Processing ...

10
DPA Resistant Software Library
DPA Resistant Software Libraries are a portfolio of unique products that provide performance optimized, quantifiable side-channel resistant security for embedded software systems with seamless integration across a wide range of applications. Our software libraries come in two main varieties, platform neutral C-code which is designed to run on any platform and optimized code for ARM Cortex platforms, providing a wide range of device design options.

11
DPA Workstation Analysis Platform
Designed for leading security chip vendors, product companies, testing labs, and government organizations, the DPA Workstation analysis platform is the world’s premier side-channel analysis plat...

12
Full flexible multi-channel AES-GCM engine up to 2Tbps
The EIP-63, high speed AES-GCM engine is a scalable high-performance, multi-channel cryptographic engine that offers AES-GCM operations as well as AES-CTR and GMAC on bulk data. Its flexible data path...

13
Interlaken FEC (ILKN FEC)
OpenFive

14
Protocol-IP-338 High-speed XTS-GCM Multi-stream Engine
The Protocol-IP-338 (EIP-338) is a scalable, high-performance, multi-stream cryptographic engine that offers XTS and GCM modes of operation for the AES algorithms on bulk data. Its flexible data path ...

15
Real-time detector of zero-day attacks on processor - Cyber Escort Unit
The end justifies the means. It seems that today s processors follow this Machiavellian precept to achieve even more impressive performances. However, this has a critical negative impact on security b...

16
Scrambled Bus
The security of a System-on-Chip depends on various tamper protections used to protect the cryptographic keys from different kind of attacks. These keys are usually transmitted as plaintext between he...

17
Secure Clock
Secure Clock IP core is a PRNG-based hardware implementation of a random clock jitter injection and/or a random clock cycle inhibition. It is intended to clock feed all desired hardware, creating a se...

18
Small, Universal and Digital Fault Injection Attack Detector - Digital Sensor
Universal fully-integrated fault attack sensor In cryptography, an attack can be performed by injecting one or several faults into a device thus disrupting the functional behavior of the device. Tech...

19
BA470 - Security Enclave IP based on RISC-V
The eSecure IP is a single subsystem for RISC-V based SoC to address key security challenges, playing the role of root-of-trust.

20
DDR Encrypter

The DDR encrypter IP Core module enables on-the-fly encryption and authentication to the external memory

It supports AXI slave/master interfaces, APB port for configuration purpose. I...


21
Fuzzy-ID - Device identification with silicon fingerprint
Tiny variations in a semiconductor manufacturing process make each transistor and each piece of silicon unique. These variations are random and uncontrollable making it impossible to construct an exac...

22
PermSRAM
A versatile nonvolatile memory macro available on foundry standard CMOS platform covering process node of 180nm to 28nm and beyond.

23
TwinBit
An embedded, true logic-based non-volatile memory solution with an extremely high endurance performance of 10K (PROGRAM) cycles.

24
Advanced Encryption Standard XTS mode IP - XIP1183B:_AES256-XTS
XIP1183B from Xiphera is a balanced Intellectual Property (IP) core implementing the Advanced Encryption Standard (AES) with 256-bit long key in XTS mode. XTS is a mode of operation for a block ciphe...

25
Advanced Encryption Standard XTS mode IP - XIP1183H:_AES256-XTS
XIP1183H from Xiphera is a high-speed Intellectual Property (IP) core implementing the Advanced Encryption Standard (AES) with 256-bit long key in XTS mode. XTS is a mode of operation for a block cip...

26
BCH based Error Correcting Code FEC
Zero latency, low gate count, low power, asynchronous BCH Code based Error Correction FEC

27
CC-100IP-PI Power Integrity Enhancement IP

The CC-100IP-PI on Chip IP Block is an on-chip adjustable Impedance Controlled Hyper- capacitor with a Capacitance Multiplication, Series Inductance Nullification, Cybersecurity Enhancement and an ...


28
CC-100IP-RF Analog and RF Sensitivity Enhancement IP

The CC-100IP-RF is a RF and Analog Frontend Sensitivity Enhancement IP Block that embeds a Hyper-Capacitor with a Capacitance Multiplication, Series Inductance Nullification, Cybersecurity Enhancem...


29
Erasure Code based on Reed Solomon Codes
Erasure Code based on Reed Solomon Codes

30
FireCode FEC Error correction bust error correction FEC
Zero latency, asynchronous, low power , low gate count FireCode FEC.

31
Generic Polar FEC Codec
Creonic has flexible Polar decoder architecture to fulfil different customer requirements. The IP core has been demonstrated on internal conferences and shows. An FPGA demonstrator is available for ...

32
Hamming Code ECC 1 bit error correction and 2 bit error detection
Hamming Code ECC

33
IPsec Security Processor
Core implements the IPsec and SSL/TLS security standard at high data rates that require the cryptographic processing acceleration.

34
Low Power Security Accelerator Engine IP
The Low Power Security Accelerator Engine IP is a complete, compact and area efficient hardware engine. It is both timing and side channel attack resistant. The Low Power Security Accelerator Engine I...

35
Reed Solomon based Error Correcting Code FEC burst error correction
Zero latency, low gate count, low power, asynchronous Reed Solomon Code based Error correction FEC

36
TESIC CC EAL5+ Secure Element IP Core
TESIC is a CC EAL5+ PP0084 proven/certification-ready secure element IP that is delivered as hard macro for plug-and-play System-on Chip (SoC) integration

37
AES Engine IP
YEESTOR s AES engine (ESAES) IP is a high-performance cryptographic engine operates in AES (Rijndael) NIST Federal information processing standard FIPS-197. It supports AES-ECB AES-XTS mode and 128/25...

38
Cronus
Cronus is a SmartNIC PCIe card and is designed for network monitoring and security applications that require high throughput and low latency. It is a unique, hardware accelerated solution that combines network monitoring capability with Security Analytics Acceleration (SAA) and content processing.

39
Geon Secure Execution Processor
Geon Secure Execution Processor delivers secure code execution by supporting two secure contexts. All code and data belonging to a secure context is cryptographically isolated in main memory, so even ...

40
Helios F1
Helios F1 is an FPGA-based Regular eXpression Processor (RXP), designed to be used as a CPU offload accelerator. The RXP runs on an Amazon FPGA Image (AFI) in an AWS EC2 F1 instance.

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