in cooperation with SemiWiki



























Where : Hyatt Hotel, Santa Clara
When : April 5th, 2018

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Silicon Intellectual Property (IP) is the vital seed of semiconductor Industry. Recognizing this fact, D&R IP SoC event Series, the unique events fully dedicated to IP in Electronic Systems, has as goal to trigger worldwide the most exciting information sharing opportunities between IP providers and IP consumers.

You just cannot miss those events.

Organized around D&R IP SoC worldwide community of 27000 active members, it is the place to meet the top professionals in this field.

You will get the latest vision of the trends in IP based Electronic Systems as well as information about the most advanced offerings from the best specialists in the field ranging from foundries, EDA vendors, IP Providers, Design House to Electronics System companies.

Get the best vision from the gurus about hot topics such as :

  • How does the IP Soc community provide key resources enabling the AI and Deep learning applications?
  • Benefits and status of the Risc5 initiative
  • IP management from IP ecosystem to Reuse: what is really innovative?
  • eFPGA why so exciting in today asic?
  • The latest and best Automotive IP ,Security IP and video IP
  • And more about interface IP, NVM...
Tentative Program - subject to modifications.


 Welcome
9:20 am IP Provider the vital seed of Electronic industry

By Gabriele Saucier
CEO & Founder
D&R
France
9:40 am The Rise of Contract Design Services

By Samir Patel
CEO
Sankalp Semiconductor Pvt Ltd
India
 AI and Deep Learning
Chairman : Gabriele Saucier, D&R.
10:00 am Embedding Artificial Intelligence into Our Lives

By Mike Thompson
Sr Product Marketing Manager
Synopsys Inc.
USA
10:20 am Intelligence everywhere - Bringing machine learning everywhere computing happens

By Vrajesh Bhavsar
Senior Segment Manager
Arm Ltd.
USA
10:40 am Break
 More about Risc5 Initiative
11:00 am The promises and pitfalls of RISC-V, from SOC Design Perspective

Organizer : Jonah McLeod, Andes Technology Corporation
Moderator : Kevin Krewell, Principal Analyst, TIRIAS Research
Panelists :
  • Ted Speers (Product Architecture and Planning Head, Microsemi Corp.)
  • Yunsup Lee (Co-Founder and CTO Sifive, Inc.)
  • Emerson Hsiao (Senior VP, Andes Technology USA Corp.)
  • Dave Ditzel (President and CEO, Esperanto Technologies, Inc.)
12:15 pm Lunch Break
 IP Management from Reuse to IP Ecosystem
Chairman : Aman Joshi, WD, a Western Digital company.
1:00 pm Foundation IP Platform(s) and IP EcoSystem Potential

By Sebastian Ventrone
Distinquish Member Technical Staff, A&D IP Program Manager, GF Master Inventor
GLOBALFOUNDRIES
USA
1:20 pm IPMS: IP Management From IP Design to Delivery up to Royalty Reporting

By Gabriele Saucier
CEO & Founder
D&R
France
1:40 pm IP Reuse for the Masses through System Design Automation

By : Bob Ledzius
Founder & CEO
Concertal Systems Inc.
USA
2:00 pm User Behavior Learning and Smart Software License Manager

By Gabriele Saucier
CEO & Founder
D&R
France
2:20 pm Break
 eFPGA an exciting opportunity
Chairman : Badawi Dweik, Lattice Semi.
2:40 pm eFPGA Virtual Array Architecture

By Cheng Wang
Sr VP Engineering & Co-Founder
Flex Logix Technologies, Inc.
USA
3:00 pm Embedded FPGA enabling 5G Infrastructure

By Mike Fitton
Senior Director, Strategic Planning
Achronix Semiconductor Corporation
USA
3:20 pm eFPGA for AI and IoT applications

By Dr. Timothy Saxe
CTO
QuickLogic Corporation
USA
3:40 pm Break
 Video IP
4:00 pm Efficient design of multi-format video decoders

By Doug Ridge
Business Development Manager
Amphion Semiconductor Ltd
UK
4:20 pm Video Encoding in the cloud

By Oliver Gunasekara
CEO & Founder
NGCodec Inc.
USA
 More innovative IP
4:40 pm Killer Apps for USB 3.1 Gen 2

By Ali Khan
VP of Product & Business Development
Corigine Inc.
USA
5:00 pm Power Optimizer IP

By Michael Hopkins
Founder & CEO
CurrentRF
 Automotive IP
Chairman : Ron Digiuseppe (Synopsys, Inc.)
1:00 pm Meeting ADAS SoC Safety Design Challenges with Active Safety Feature-Enabled IP

By Rishi Chugh
Head of Marketing, Interface IP
Cadence Design Systems, Inc.
1:20 pm Automotive Challenges Addressed by Standard and Non-Standard Based IP

By Meredith Lucky
VP of Sales
CAST Inc.
USA
1:40 pm Embedded Analytics and Automotive security

By Rupert Baines
CEO
UltraSoC Technologies Ltd
UK
2:00 pm Break
 Security IP
2:20 pm Enhanced security and performance through cryptographic offloading and acceleration for cloud based computing

By Pieter Willems
Marketing Manager Security Products
Silex Inside
Belgium
2:40 pm Embedding security step-by-step

By Ron Keidar
US FAE
INSIDE Secure
USA
3:00 pm Enhancing existing IoT SoC chip solutions with "Drop-In" NSA Suite B security

By Chuck Gershman
Strategic Development Director
Intrinsix Corp.
USA
3:20 pm Break
 Enabling technology for AI SoC
3:40 pm Enabling Technology for the Cloud and AI - One Size Fits All?

By Lisa Minwell
Sr. Director IP Marketing
eSilicon Corporation
USA
4:00 pm 16 nm Multi protocol Serdes for an AI⁄ Machine Learning SoC

By Mahesh Tirupattur
Executive VP Sales, Marketing & Operations
Analog Bits, Inc.
USA
 NVM in SoC architecture
4:20 pm FPGA based Configurable NVMe SSD Platform

By Amit Saxena
VP of Engineering
Mobiveil, Inc.
USA
4:40 pm More Than Just eFlash: a Roadmap of How MRAM Will Change Soc Architectures

By Nicholas Hendrikson
Director of Engineering
NVMEngines
USA
 Startup Forum
5:00 pm CMOS Energy Efficiency from harvested data - Circuit Opportunities for Machine Learning

By Azeez Bhavnagarwala
Metis Microsystems, LLC
5:20 pm Multi-Processing in small FPGA's

By Al Schneider
Schneider Software Systems

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