Industry Expert Blogs

How to reduce the risk when making the shift to RISC-V

- Codasip GmbH
Nov 18, 2022

In conversation with Vijay Krishnan, Intel Corporation, and Rupert Baines, CMO at Codasip

With the Intel® Pathfinder for RISC-V* program, Intel launched a development environment that enables companies of all sizes to start their RISC-V journey. Codasip makes its L31 RISC-V embedded core available to the embedded community through the program.

We asked Vijay Krishnan, Intel Corporation, and Rupert Baines, CMO at Codasip, to tell us more about this.

VIJAY, WHAT IS THE RISK WHEN MAKING THE SHIFT TO RISC-V?

There is real risk and then there is perceived risk. Regarding the former, any architectural transition adds complexity, but with RISC-V the entire hardware and software ecosystem is coming together in a manner which minimizes the real risk, while unleashing the long-term value that comes with an open, modular and modern instruction set architecture. The presence of cores like the Codasip L31 are making it easier and easier for customers to make that transition so they can reap the benefits of RISC-V. Sensors, security IP/software, IoT middleware and cloud connectivity available within the Intel Pathfinder for RISC-V IDE all help to mitigate perceived risk by demonstrating end-to-end capabilities at the pre-silicon stage.

RUPERT, DO YOU AGREE WITH THIS, AND IS RISC-V RISKY?

Well, the cool thing about RISC-V is that it is an open standard, and that brings so many possibilities. But that can also be a challenge! Endless possibilities make it harder to make a choice and the evolving ecosystem can be hard to navigate.

Intel has blazed a path with Intel Pathfinder for RISC-V by making a first selection of recommended vendors, and from that stamp of quality, companies can explore and evaluate what best fits their needs.

As a key RISC-V processor IP vendor, it was obvious for Codasip to be part of the Intel Pathfinder for RISC-V ecosystem. Our L31 core is quite versatile so we chose to make it available to the wider embedded community through the program. It is a low-power, general-purpose, embedded RISC-V core that balances performance and power consumption. From IoT devices to industrial and automotive control, or as a deeply embedded core in a larger system, it brings local processing capabilities into a compact area.

WHO IS GOING TO BENEFIT FROM THIS INTEL & CODASIP PARTNERSHIP?

Vijay: The initial beneficiaries are end-user segments addressed by the Codasip L31 core. Over time we hope Intel Pathfinder for RISC-V will include support from a broader range of Codasip cores. By harnessing our combined capabilities, we see a tremendous opportunity to accelerate the transition to RISC-V, thereby establishing it as a third mainstream compute architecture after x86 and Arm.

Rupert: Companies of all sizes, really. From SMEs to start-ups and bigger players. We give everyone access to high-class silicon ready proof points to get started with their RISC-V journey in a standard and stable environment. If they wonder whether they should go with our L31 core, they can see their use case brought to life. With Intel Pathfinder for RISC-V, our core can be integrated with a growing set of complementary IPs, multiple operating systems, and toolchains for IoT and embedded applications.

HOW IS THE RISC-V ECOSYSTEM DOING TODAY?

Vijay: In addition to being open and modular, RISC-V is free and easily licensable. In less than 10 years since its inception, RISC-V has made remarkable progress, driven largely by a well-knit ecosystem that includes academia & research in addition to a breadth of commercial organizations. The opportunities are vast, and based on what we have seen to date, the RISC-V market will reward organizations that not only build competitive products, but also foster collaborative models within the ecosystem.

Rupert: The RISC-V community is growing rapidly and continuously gaining market traction. It is attracting everyone, from university researchers to major industry players. There have been new processors and new ISAs in the past. But what is different about RISC-V is the ecosystem, a critical factor in the success of a processor architecture. More and more players are joining, more and more software and tools are available, broadening the adoption of the ISA. This in turn is attracting more ecosystem partners in an accelerating virtuous spiral, and it is that spiral that is driving the success of RISC-V, in which Intel and Codasip play a major role for the embedded industry.

HOW IS THIS PARTNERSHIP HELPING COMPANIES MAKE THE SHIFT TO RISC-V?

Vijay: By combining Codasip RISC-V IP with the Intel Pathfinder for RISC-V developer tools, we are making it easier for customers to go from product concept to a mature platform that includes silicon and software. Intel Pathfinder for RISC-V combines RISC-V IP with complementary security IP, accelerators for AI/ML, Vision and Audio processing, as well as sensor and middleware integration, thus providing an accelerated software development path for customers that reduces time to market, cost and complexity/risk.

Rupert: The program removes the barrier to the adoption of RISC-V by providing a level of standardization that can make RISC-V adoption easy with some level of consistency for the software developer community. By collecting vendors of different types, the program can kickstart the development of a new system by bringing together all the great capabilities already out there, including L31. You can instantly start an IoT application based on our L31 core, combine it with other IP, integrate security from Crypto Quantique, and verify it all using Siemens EDA even before committing to silicon.

Collaboration is key.

Those who collaborate are better set for success in RISC-V than those who don't. Thanks to an ecosystem coming together, the risk of RISC-V is reduced, and you can easily explore options when you are ready to make the shift. Codasip and Intel are exploring further possibilities for collaboration, and you will see more offerings going forward, always with quality and ease of use in mind.

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