Industry Expert Blogs
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Introduction to Tessent Multi-DieVinayashree Hiremath - Siemens - Tessent Embedded AnalyticsJun 02, 2024 |
With the latest developments in electronic industry to support revolutionary complex systems such as Autonomous vehicles or AI products/chips system-in-package becomes inevitable. System-in-package, SiP which is "more-than-Moore's law", incorporates multiple dies inside one package making heterogenous integration possible. In a SiP, each die connects to other dies using either 2.5D or 3D interconnect technology.
While in 2.5D ICs chiplets are integrated on an interposer layer horizontally, in 3D ICs the chiplets are stacked vertically. Tessent provides design steps to insert test logic for each die, mechanism to access individual die, to perform die-die interconnect test and so on.
In 2.5D IC, we insert DFT logic in the dies, make the whole package compliant with IEEE 1149.1 standard, as well as insert the Boundary Scan in the die in order to improve the Boundary Scan performance after integration to the package. Memory BIST and BISR can also inserted in parallel with the Boundary Scan logic. Additionally, we insert test logic instruments for logic test and ATPG. The SSN allows daisy chaining of the dies and is recommended for flexible testing of each die.
In 3D IC, we support IEEE 1838 standard that describes the test access architecture and provide the required serial access mechanism using Primary Test Access Port (PTAP) or Secondary Test Access Port (STAP). Flexible Parallel Port (FPP) access mechanism can be used to distribute volumes of scan patterns. Tessent SSN can be used as the Flexible Parallel Port (FPP) for the standard.
We can also use 3D and 2.5D methodologies together in the same package to create 5.5D design, which benefits from both methods. More information on core level and die-level DFT insertion and scan insertion can be found in the Tessent Multi-die User's Manual. A support kit on 2.5D IC design can be accessed here, 2.5 Flow for Multi Die designs (siemens.com)