时间：2025 年 9 月 11 日
地点：上海淳大万丽酒店,中国上海浦东联洋新社区迎春路719号
Join D&R IP SoC China 25 !! A worldwide connected Event !!
Co-organized with:
D&R IP-SoC China 2025 Day 是中国首个完全致力于IP（硅知识产权）和基于IP电子系统的独特全球性活动。
作为芯片设计业创新的种子，IP-SoC展商受邀展示他们最新的产品和服务，并分享他们对半导体行业下一步创新的展望。
IP用户可以一目了然地查看最新的技术趋势和令人兴奋的创新IP/SoC产品。通过全局视角，电子系统领袖可以识别颠覆性创新，带来新的细分市场增长。
本活动将是一次线下面对面会议。为了增强市场关注度，演讲材料和视频将同时发布在 www.design-reuse-china.com 和Youku上。
有任何问题吗？请与我们联系。
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9.00 am
Introduction
Chairperson: Bulu Xu, SSIPEX
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IP vendor the seed of innovation in the semiconductor world
Gabrièle Saucier
CEO
Design And Reuse
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Status and Trend of China's IP
Dr. Xu
SSIPEX
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灿芯半导体——您值得信赖的一站式IP和SoC平台解决方案合作伙伴
饶青
IP Project Director
Brite Semiconductor
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Break
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10.20 am
Chiplets and Connectivity
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UCIe-S v2.0 PHY IP：从仿真到流片的稳健设计方法与硅上实测结果
We will present our UCIe test results along with an overview of our development environment and methodology. This session will highlight key findings from our UCIe PHY testing, demonstrating performance and interoperability. Additionally, we will sha re insights into our structured development workflow, verification strategies, and collaborative environment designed to deliver high-quality, reliable IP solutions.  ... 
Roger Han
Strategy & Marketing Team Leader
Qualitas Semiconductor
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《晟联科IOD，Scale-up生态“战国时代”的优选方案》
柳雷
解决方案经理
eTopus Technology Inc.
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Highspeed Connectivity Solutions for 22nm Tech Nodes
New applications in networking, in communications like 5G/6G and mmWave or in automotive with radar/lidar require high-speed data connectivity. This incurs data rates bigger than 20 Gbps per lane. These applications typically require chips that are p roduced in mainstream tech nodes, like GF 22DFX. When many data lanes are applied and active the power consumption of SerDes-based connectivity becomes an issue and can break an intended architecture. EXTOLL�s technology provides solutions for highest speeds at lowest power consumption enabling new future-proven systems. ...
Robert Kong
Extoll GmbH
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解锁算力瓶颈：DRAM、SerDes、Chiplet IP 如何重塑高性能芯片架构
贾仪彬
IP&SoC Solution Architecture
Innosilicon
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为可信赖的系统级封装构建Chiplet 安全
Chiplets are a new way to design in electronics: creating an application simply requires to stitch together already existing chiplets in a so-called System-in-Package (SiP). Cadence has already taped-out a chiplet targeting automobile industry, in 3 nm TSMC process. It embedded Secure-IC IPs to secure it and allow for a secure SiP assembly. Chiplet is the next paradigm for automotive market and datacenters, which are both software defined hence require a uniform hardware. In this paper, Secure-IC explains how security is enabling secure assembly of chiplets. Besides, we announce the Protection Profile drafting effort that we have undertaken. ...
Shengnan WANG
General Manager China
Secure-IC
Online Only
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1.00 pm
Analog and Memory IP
Chairperson: Alex ZOU, Innosail
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Advancing Power Telemetry
Julian Hu
VP, China Sales
Movellus, Inc.
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SLM PVT 监控器 IP 概述
Synopsys Silicon Lifecycle Management (SLM) PVT Monitor IP sets the industry standard for excellence. We provide hard IP that is complemented by dedicated PVT-Controller soft IP, enabling the creation of desirable monitoring subsystems. Our highly di fferentiated IP offers unparalleled accuracy, broader operating temperature and voltage ranges compared to the competition and provides customers with the confidence of fully silicon-verified solutions, accompanied by comprehensive silicon reports. As advanced nodes continue to evolve, the need for monitoring is expanding. Synopsys SLM PVT Monitor IP addresses the growing demand for process-related electrical and thermal condition data collection across all phases of an SoC's lifecycle—from testing to real-time mission mode operation. Staying attuned to our customers' needs, we are actively expanding our portfolio with new monitoring subsystem solutions and increasing foundry coverage. The SLM PVT Monitor IP now offers expanded foundry coverage, including Samsung, in addition to TSMC's latest processes. These features make Synopsys SLM PVT Monitor IP highly differentiated, offering a unique value proposition unmatched by competitors in delivering a comprehensive, end-to-end total solution. ...
Liqiong Yu
Application Engineer
Synopsys, Inc.
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Semiconductor IPs for Memory, Flash storage and wireless applications
Ravi Thummarukudy
CEO
Mobiveil Inc.
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Break
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2.20 pm
Memory Interface
Chairperson: Alex ZOU, Innosail
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LPDDR 内存子系统的广泛应用
Minlin Fan
China Country Manager & VP of Sales
OPENEDGES Technology, Inc.
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解锁边缘侧生成式AI的未来：LPDDR如何赋能可扩展的高效智能
随着生成式 AI不断重新定义创造力和自动化的边界，其真正价值在于为实 ;际部署场景优化推理能力——尤其是在边缘测。本次演讲将探讨推理如何成为关键推动因素，助力响应迅速、高效且可扩展的生成式 AI 体验。我们将剖析 LPDDR 内存技术如何凭借其在高带宽、低延迟和成本效益之间的独特平衡，完美契合边缘 AI 应用——从智能摄像头、工业传感器到自动驾驶系统。本次演讲将重点介绍架构设计考量、性能基准测试和开发案例研究，展示 LPDDR 如何赋能边缘推理芯片，以满足生成式 AI 工作负载的需求。 ...
Kai Zhao
SPE Field Applications Engineering
Rambus, Inc.
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Break
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3.20 pm
Automotive Solutions
Chairperson: Alex ZOU, Innosail
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生态驱动创新：GPU与RISC-V的协同赋能汽车智能化
Abstract: 1. RISC-V have a lot of potentials now and in the future, automotive is one of it target market. 2. Imagination (IMG) as GPU IP global leading provider, continue work closely with/contribute in RISC-V ecosystem 3. automotive comput ing: scalable, safe and open 4 automotive design points: flexibility , future workloads scoping, innovation for differentiation. 5. IMG GPU are essential for real time visualization , sensor fusion, display pipeline parallel AI workloads and safety-critical rendering. 6. IMG work closely with ecosystem partners and RISC-V communities to enhance vertical cooperation for auto market ...
黄音
Head of Business Development
Imagination Technologies Group Ltd.
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DSP在车载SoC领域的成功应用
介绍Cadence DSP在车用SoC芯片中的应用趋势和价值，包括在ADAS和座舱芯片上的视觉 、雷达、AI以及娱乐子系统中的应用。 ...
王桐
Sr. Application Engineer
王桐
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1.00 pm
人工智能
Chairperson: James Liu, Shanghai Innovation Center
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用于 AI 纵向扩展和横向扩展基础设施的接口 IP
LLM的火热推动了AI基础架构规模化和横向扩展的需求。Cadence紧跟市场需求，৻ 2;供极具竞争力的接口IP，助力产业快速发展。 ...
何金强
Cadence Sr Principal Application Engineer
Cadence Design Systems, Inc.
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神经视频处理IP-视频AI引擎
Presentation of Allegro DVT's NVP300 Neural Video Processor IP and how it can serve as the AI Engine for Video.
韦裕京
VP Sales & Country Manager APAC
Allegro DVT
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端侧AI新纪元
各类设备上的 AI 功能正在迅速演进，但AI系统设计者依然面临性能、效率 982;灵活性的多重挑战。Imagination凭借其长期深耕低功耗 GPU 的经验，成功实现了GPU架构对图形与AI的灵活支持。E-Series 结合了 GPU 的可编程性与 AI 性能的飞跃，为边缘智能（Edge AI） 系统开发者带来了极具吸引力的解决方案。 GPU作为可编程处理器，通过面向未来的架构设计，使设备能够持续应对 AI、计算和图形工作负载的演进。本次演讲将介绍E-Series神经核心如何通过在 GPU 内部深度集成 AI 加速能力，与更广泛的 GPU 及异构计算软件生态实现无缝协同 —— 其算力可通过OpenCL 等主流 API直接调用，开发者借助oneAPI、Apache TVM 或 LiteRT等开放标准工具，能轻松将工作负载迁移至神经核。Imagination的计算库与高度优化的图形编译器，进一步释放了GPU的全部潜能。 ...
孙千喆
Sr. Application Engineer Manager
Imagination Technologies Group Ltd.
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Break
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2.20 pm
Artificial Intelligence (part 2)
Chairperson: James Liu, Shanghai Innovation Center
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芯原高性能Vitality GPU-AI IP赋能AI PC和云游戏服务器
VeriSilicon’s next-generation Vitality GPU-AI IP delivers a comprehensive solution that integrates high-performance graphics rendering with AI acceleration, tailored for AI PCs and cloud gaming servers. Through architectural optimization, the IP significantly enhances computational performance and energy efficiency, supporting a wide range of parallel workloads and complex graphics processing to meet the diverse demands of AI and gaming applications. Backed by VeriSilicon’s rich IP portfolio and its unique SiPaaS (Silicon Platform as a Service) business model, the company offers customers flexible and efficient one-stop custom silicon services, enabling rapid adaptation to evolving market needs and driving continuous innovation and high-quality development across the semiconductor industry. ...
张慧明
GPU/显示产品高级副总裁
芯原微电子（上海）股份有限公司
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新代互连技术助力未来 AI 基础设施扩展
左庆华
首席应用工程师
Synopsys, Inc.
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RISC-V 向量计算赋能 AI 发展
范涛
商务拓展总监
Sifive, Inc.
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Break
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3.40 pm
Security Solutions
Chairperson: James Liu, Shanghai Innovation Center
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How to Build Robust Security into Your AI SoC Designs
Matthew Ma
Senior Staff FAE
Synopsys, Inc.
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使用MACsec保护传输中的数据
随着企业采用高性能计算、AI工作负载以及云-边缘架构，保护网络内部及 ;跨网络的传输中的数据安全变得日益重要。本次演讲将探讨一项应对这一挑战的关键技术：MACsec（媒体访问控制安全）。演讲将深入剖析 MACsec 如何保障第二层以太网通信免受窃听、重放和中间人攻击等威胁。此外，鉴于以太网技术在应用领域的持续扩展和普及，还将讨论从数据中心到汽车市场的 MACsec 当前及未来的实现方式。 ...
Kevin Zhang
SPE Field Applications Engineering
Rambus, Inc.
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通过功能监控推进SoC调试和优化
随着现代片上系统（SoC）设计发展到前所未有的复杂程度，特别是随着高 ;性能计算、生成式人工智能和多芯粒技术的出现，传统的调试和测试解决方案已经不足以满足当前的质量、可靠性、性能和预测性维护要求。为了应对这些挑战并加快上市时间，同时保持系统性能和可靠性标准，一个可扩展的嵌入式功能监视器系统，Tessent Embedded Analytics，提供了在实际软件执行过程中对设备行为的全方位可见性。 ...
Wei Zheng
Staff Application Engineer
Siemens - Tessent Embedded Analytics
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4.30 pm
Do not miss the Lucky Draw sponsored by
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