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Program

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IP-SoC 2017 will be the 20th edition of the working conference fully dedicated to IP (Silicon Intellectual Property ) and IP based electronic systems.

This year is a special edition as we celebrate jointly D&R 20th anniversary.

Therefore a special keynote session will be dedicated to visionary talks covering the past 20 years history in the IP SoC domain and even more challenging predicting the next decade... You just cannot miss it

IP SoC 2017 Tentative Program

User Group meeting and seminar : December 5th
DAY 1 : December 6th
DAY 2 : December 7th

DAY 0: Tuesday December 5th, 2017

Join D&R User Group meeting and seminar on December 5th at 5:00 pm

This meeting is a brainstorming meeting to explore how D&R services can better serve the worldwide IP community.

5:00 pm	D&R website and News Alerts D&R Websites attracts an unique audience worldwide for 2 decades in the IP SoC arena. The meeting intends to collect wishes as well as to answer frequently asked questions such as : What are the roles of D&R websites? (www.design-reuse.com, www.design-reuse-embedded.com, www.design-reuse.cn) Which products are listed on D&R websites? Is there any qualification? Can a company member look at IP without being harassed by providers alerted by a lead Most important, what are the needs D&R should fulfill to serve the IP SoC market?
	What's new in IPMS™ latest version (D&R Intranet IP Management System) for IP providers ? IPMS™ is the D&R IP intranet management turnkey solution for monitoring IP from design repository to client delivery and providing life cycle support . Some FAQ and others will be addressed IP or IP version listing: How to synchronize IP web list with a management list? How to Insert web GUI How can the bug list be synchronized with an IP list and ensure the best customer support? Which API to design DB? More about Client Project centric IP development flow Learn more on how to guarantee a safe worldwide delivery process
	What's new for IP Consumers ? What support in terms of "Where Used" , IP tracing in product and delivery up to financial follow up? How can an IP management platform be synchronized with "IP in Product Tracing"? How to be in Sync with customer product delivery corporate platform What’s new about IPMS unique Royalty engine preventing audit issues?
	What’s New in D&R software License Management For a number of years now, Design & Reuse is delivering an industry-leading integrated solution for corporate global Software License Management covering license administration, license remix/renew, finance and purchasing management. Which administrative features are supported ?
7:00 pm	Welcome drinks

DAY 1: Wednesday December 6th, 2017

Welcome to D&R 20th anniversary
9:00 am	Welcome - Two decades and what next? By Gabriele Saucier CEO & Founder D&R France
9:20 am	Congratulations D&R By Dr. Aart de Geus - Video Chairman and Co-Chief Executive Officer Synopsys Inc. USA
9:30 am	In the beginning there was Arm By Robin Saxby Founder Arm USA
9:40 am	The path to 100 billion chips - from instruction sets to CPUs By Phillip Burr Director Product Management Arm Ltd. USA
10:00 am	Break
The Past and the Next Decade Vision Chairman : Charles Janac, ArterisIP
10:30 am	Fortune Behind the Great Wall: China IP to IC industry review and outlook 2017 By Mark Ma GM Shanghai Jiatao Industrial Co., LTD. China
10:50 am	Changing dynamics in the semiconductor industry By Eklovya Sharma Head, Sankalp Marketing Sankalp Semiconductor India
11:10 am	The Reusable IP Revolution and How a Small Company Took Advantage By Bill Finch Senior VP CAST Inc USA
11:30 am	Break
Foundry vision Chairman : Mahesh Tirupattur, Analog Bits
12:00 pm	Foundry market changes and Samsung Foundry's roles By Michael Choi Project Leader of Data Converter IP Development Samsung South Korea
12:20 pm	How Decades of research lead to new technology process : The FDSOI history and its future By Philippe Flatresse Business Development - SOI expert Soitec France
12:40 pm	FDXcellerator and the growing 22FDX ecosystem By Gerd Teepe Director of Marketing for Europe Global Foundries Inc. Germany
1:00 pm	Lunch Break
From IP to SoC: What is the trend Chairman : Philippe Quinio, STMicroelectronics
2:00 pm	Why analog IP are the seed of the IP SOC world By Mahesh Tirupattur Executive VP Sales, Marketing & Operations Analog Bits, Inc USA
2:20 pm	Decades of IP Innovation to Accelerate Silicon Success By Luis Laranjeira R&D, Director Of Engineering Synopsys Inc. Portugal
2:40 pm	Interconnect IP, Where we have been and where we are going. By Charles Janac CEO ArterisIP USA
3:00 pm	RISC-V: What the industry needs now? By Roddy Urquhart Director for EMEA Business Development Codasip Ltd. UK
3:20 pm	How and why eFPGA will become pervasive over the next decade By Geoffrey Tate CEO Flex Logix Technologies USA
3:40 pm	Break
New Business Model and new infrastructure Chairman : Mark Ma,GM,Shanghai Jiatao Industrial Co.
4:10 pm	How to design a SoC and get Arm CPU IP for no upfront license fee By Phillip Burr Director Product Management Arm Ltd. USA
4:30 pm	Next Generation IP Management Infrastructure: What's the vision? By Gabriele Saucier CEO & Founder D&R France
4:50 pm	Break
Automotive IP and Software Chairman : Gerd Teepe, Global Foundries Inc.
5:20 pm	Meeting ADAS SoC Safety Design Challenges with Active Safety Feature-Enabled IP By Rishi Chugh Head of Marketing , Interface IP Cadence Design Systems, Inc. USA
5:40 pm	Safety Verification and Software Aspects of Automotive SoC By Singh Pankaj Sr. Manager Infineon Technologies AG India
6:00 pm	eFPGA is the key solution for Automotive embedded systems By Imen Baili Sales Application Engineer Menta France
6:20 pm	Break
6:45 pm	Wine Tasting Party Sparkling Wines of the world (SST-Microchip) Napa Valley Wine (Analog Bits) French Wine - the Must (D&R)
7:30 pm	D&R 20th anniversary French Touch Dinner

DAY 2: Thursday December 7th, 2017

Welcome to the Designer World Chairman : Eklovya Sharma, Sankalp Semiconductor
8:30 am	Why Approved Design Centers ? Arm initiative By Debbie Dekker Arm Approved Program Manager Arm USA
8:50 am	Cost-effective design of next generation ultra-low power SoCs - More intelligent design needed By Frederic Renoux eVP Sales et Marketing Dolphin Integration France
9:10 am	Break
Power Management and IoT vision Chairman : Philippe Flatresse, Soitec
9:30 am	Low power embedded flash for IoT By Chris Brown General Manager Microchip Technology Inc. USA
9:50 am	Achieving Low power with Active Clock Gating for IoT in IPs By Chaitanya Kamasani ASIC DESIGN ENGINEER -II Synopsys Inc. INDIA
10:10 am	Energy Harvesting System implementing an Adaptive Dynamic Power Management Algorithm for Wearables and IoT applications By Loic Zahnd CSEM SA. Switzerland
10:30 am	Break
Security Chairman : Singh Pankaj, Infineon Technologies AG
10:45 am	Embedding Security Step by Step By Jérôme Allard Silicon IP Product Manager Inside Secure France
11:05 am	Concerned about security ? Don't leave your memories unprotected By Ilan Sever Subsidiary General Manager Dolphin Integration Inc ISRAEL
11:25 am	How to ensure car security using protected hardware By Ismail Guedira Sales & Marketing Engineer Secure IC France
11:45 am	Break
Design methodology Chairman : Phillip Burr, Arm Ltd.
12:00 pm	From UPF to Power Management: The Long and Winding Road. By Dustin Peterson PhD student University of Tuebingen Germany
12:20 pm	A power management unit for ULP SoC including ultra-low power Bluetooth 5 radio By Nicola Scolari Expert CSEM SA. Switzerland
12:40 pm	Modular Design of level -2 cache for flexible IP configuration By Thang Tran Principal Engineer Synopsys Inc. USA
1:00 pm	Lunch Break
Innovative IP in FD-SOI Technology Chairman : Patrick Blouet, STMicroelectronics
1:50 pm	Fast Estimation Approach for Statistical Eye Diagram in 28nm FD-SOI Technology By Abdelgader M. Abdalla Instituto de Telecomunicações, University of Aveiro Portugal
2:00 pm	Low noise low frequency amplifier in 28nm FDSOI By Wieslaw Kuzmicz professor Warsaw University of Technology Poland
2:10 pm	Clockless circuit design in FDSOI By Marc Renaudin CTO Tiempo France
2:20 pm	Fine Body Biasing Island Strategy in FD-SOI By Rodrigo Iga Research Engineer TIMA Laboratory France
IP SoC design Chairman : Luis Laranjeira, Synopsys Inc.
2:30 pm	A low-latency, high-performance versatile SerDes Interface IP By Mondrian Nuessle CTO Extoll GmgH Germany
2:50 pm	A design of High Efficiency Combo -Type Architecture of MIPI D-PHY and C-PHY By Ian Lee Professional Engineer LG Electronics South Korea
3:10 pm	Advanced wireless IP Cores By Sudhir Singh Principal Wireless Research Engineer Callaghan Innovation New Zealand And Chatu Lokuge Business Solutions Specialist Callaghan Innovation New Zealand
3:30 pm	A PVT compensated 0.5V near -treshold microcontroller System-on-Chip By Dr. Marc Pons Senior R&D Engineer CSEM SA. Switzerland
3:50 pm	Break
System Design Chairman : Rishi Chugh, Cadence Design Systems, Inc.
4:00 pm	Full 360 Video 3d Sequence Analysis and Radar SAR for Scene 3D Understanding for space and road application By Miguel Antonio Ojeda Moreno Engineer Facultad de Ingeniería - UNLZ Argentina
4:20 pm	Embedded Vision FPGA image processing and alternatives By Werner Feith CEO Sensor to Image GmbH Germany
4:40 pm	Hardware Acceleration in data centers. How IP vendors could benefit from? By Jérôme Rampon CEO and co-founder Algodone France
5:00 pm	Give away

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