D&R News Alert
January 13th, 2024
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Welcome to the issue of January 13th, 2024 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

AlphaWave Semi
64G UCIe D2D PHY and Controller Subsystem

• Fully integrated and highly configurable subsystem: PHY and Controller
• Builds on the success of the most recent 36Gbps UCIe IP subsystem
• 24G silicon-proven with advanced package (2.5D) and standard package (2D)
• Per-lane health monitoring and full DFT features
• In-house 2.5D/3D packaging expertise
 Learn more at awavesemi.com>>

Foundry and Technology News
■ First full wafer-scale fabrication of electrically-pumped GaAs-based nano-ridge lasers on 300 mm silicon wafers
Chiplets, Multi-die
■ Multi-Die Health and Reliability: Synopsys and TSMC Showcase UCIe Advances
Design Platform
■ Exostiv Labs Unveils AMD Versal Adaptive SoC Device Support for Exostiv and Exostiv Blade Platforms
Mirabilis
Webinar: Simulating Auto Systems & E/E
architectures for power and performance
using VisualSim
Estimating latency and power for different use-cases in Systems, ECU and Networks
When : 23rd January, 2025.

• Session 1: 9:00 AM CEST / 12:30 PM India / 4:00 PM Japan, Korea / 3:00 PM China
• Session 2: 10:00 AM PDT / 1:00 PM EDT

GPR IP
■ Alphacore's Digital CMOS Impulse Ground-Penetrating Radar (GPR) Transceiver ASIC
RISC-V
■ Imagination quits RISC-V CPU business to focus on GPUs and AI
■ RISC-V in AI and HPC Part 1: Per Aspera Ad Astra?
Artificial Intelligence
■ BrainChip Brings Neuromorphic Capabilities to M.2 Form Factor
■ Intel Is Raining Edge AI Processors at CES 2025
■ Samsung invests in neural sensor startup Pison
Automotive
■ M31's 12nm GPIO IP Adopted by C*Core Technology, Powering Innovation in Advanced Process Automotive Chips
■ Automotive Safety Now Requires Data Security
■ Chiplet technology and advanced SoCs are shaping the future of software-defined vehicles
Space
■ NASA Awards Alphacore Four Contracts for Radiation Hardened Microelectronics Innovation
Partner News
■ EU approves Synopsys' $35 billion Ansys deal under conditions
■ Weebit Nano Turns 10: Only the Persistent Survive
Business News
■ Ansys sells power design tool to Keysight in Synopsys deal
■ TTTech divests strategic stake in landmark transaction to NXP to fuel future growth with technology investments in core business






Synopsys PCIe 5.0 PHY IP for TSMC N3P
• Physical Coding Sublayer (PCS) block with PIPE...
• Supports PCIe 5.0, 4.0, 3.1, 2.1, 1.1 encoding...

New IP
• Multi-protocol wireless plaform integrating Bluetooth Dual Mode, ... by CEVA
• UCIe-S PHY, Standard Package by Egis Technology Inc
• PCIe 6.2 Switch IP Controller by PrimeSoC Technologies
• ONFI 4.0 NAND Flash PHY upto 800Mbps by Brite Semiconductor

What they said at
IP SoC EU 24

Interview with Ettore Antonino Giliberti - Senior Staff Application Engineer - SmartDV Technologies

Innovating the Future with SOIL: Next-Gen IPs, Transfer from Research to Silicon
Damian Panter, Fraunhofer

From silicon to the use cases, SOIL as a test bench for automotive applications
Leonardo Govoni, AED Vantage GmbH

Designing SOC with ABX® - Challenges and Solutions
Florian Bilstein, Director Design Service, Racyics GmbH

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