Search Solutions  
17 "RISC-V Platforms" SoCs

RISC-V SOC Platform
A SOC development platform for RISC-V based designs

Security Enclave IP based on RISC-V
The eSecure IP is a single subsystem for RISC-V based SoC to address key security challenges, playing the role of root-of-trust. The module is highly flexible and fits all applications of the heteroge...

AHB-Lite PLIC - RISC-V Compliant Platform Level Interrupt Controller
Fully Parameterized & Programmable Platform Level Interrupt Controller (PLIC) for RISC-V based Processor Systems supporting a user-defined number of interrupt sources and targets, and featuring a single AHB-Lite Slave interface

Digital and mixed-signal IP and ASIC RISC-V reference design for USB Type-C/PD power adapter/charger

IQonIC Works USB-C/PD power adapter IP includes components required to build an integrated programmable power supply (PPS) charger solution.

The USB Type-C source controller detects connectio...

NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
Truechip's NoC Silicon IP provides chip designers and architects with an efficient way to connect multiple TileLink based master and slave devices with reduced latency, power, and area. NoC Silicon IP...

RISC-V debug solutions

The RISC-V open source instruction set architecture is now being widely adopted in a variety of applications. As a member of the RISC-V Foundation, Siemens is a leading player in defining and imple...

RISC-V Platform-Level Interrupt Controller (PLIC) IP
IQonIC Works RISC-V PLIC IP is a platform-level interrupt controller conforming to the RISC-V PLIC specification, for use in systems with a large number of interrupt sources and multiple processor targets for interrupt delivery.

IQonIC Works RISC-V Timer IP comprises a suite of timers, each conforming to the RISC-V standard machine timer specification.

Ultra-low-power RISC-V based GPU Processor
NEOX™ is a parallel multicore and multithreaded GPU architecture based on the RISC-V RV64C ISA instruction set with adaptive NoC. The number of cores varies from 4 to 64 organized in 1-16 cluster elem...

AndeSight IDE
AndeSight™ has Standard, MCU, RDS and Lite versions and is an Eclipse-based integrated development environment that provides an efficient way to develop embedded applications of the target systems on AndesCore™ based SoC platforms.

MIPI I3C Master RISC-V based subsystem
RISC-V based MAXVY MIPI I3C master interface has been developed to ease sensor system design architectures in mobile wireless products by providing a fast, low cost, low power, two-wire digital interf...

RISC-V (pronounced risk-five ) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V ISA delivers a new level of free, ext...

The IObundle UART is a RISC-V-based Peripheral written in Verilog, which users can download for free, modify, simulate and implement in FPGA or ASIC. It is written in Verilog and includes a C software...

RISC-V-based SoC template
IOb-SoC is a RISC-V SoC template written in Verilog, which users can download for free, modify, simulate and implement in FPGA or ASIC. It supports stand-alone and booting modes, and can use internal ...

riscvOVPsim - RISC-V Instruction Set Simulator
The riscvOVPsim ISS is an ideal starting point for an embedded software development project.

SCR, Syntacore s Family of Customizable Processor IP
State-of-the-art, synthesizable microprocessor core IP with RISC-V ISA: from the minimalistic MCU core for the deeply-embedded applications to the 1GHz+ Linux-capable application cores with SMP suppor...

RISC-V Acceleration Factory
A complete product suite for integrating, verifying, and debugging embedded systems to increase software speed-power ratios 10 to 100 times.


Partner with us

List your Products

Suppliers, list and add your products for free.

More about D&R Privacy Policy

© 2022 Design And Reuse

All Rights Reserved.

No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse.