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RISC-V Catalog
 RISC-V Platforms (20)
 RISC-V Processors (91)
 RISC-V Verification (4)
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115 "RISC-V" SoCs

1
IMG RTXM-2200

RTXM-2200 is the first core from the Catapult range. It's a highly scalable real-time, deterministic, 32-bit embedded CPU, that is feature-rich and flexible in design for mainstream devices. It...

2
Security Enclave IP based on RISC-V
The eSecure IP is a single subsystem for RISC-V based SoC to address key security challenges, playing the role of root-of-trust. The module is highly flexible and fits all applications of the heteroge...

3
64-bit RISC-V application processor core with 7-stage pipeline

The A70X is a powerful 64-bit RISC-V application processor aimed at systems running Linux. The core has an in-order 7-stage pipeline enabling greater than 1 GHz frequencies in 22nm HPC.

The...

4
64-bit RISC-V application processor core with L2 cache coherence
The A70X is a powerful 64-bit RISC-V application processor aimed at systems running Linux. The core has an in-order 7-stage pipeline enabling greater than 1 GHz frequencies in 22nm HPC. The core incl...

5
Compact efficient 64-bit embedded RISC-V processor
The Bk5 is an entry level, compact, efficient 64-bit embedded RISC-V processor aimed at embedded systems requiring a large address space.

6
Compact RISC-V Processor - 32 bit, 3-stage pipeline, 16 registers

The L10 is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requirements. The core has a 3-stage pipeline and with 16 general purpose regist...

7
Compact RISC-V Processor - 32 bit, 3-stage pipeline, 32 registers

The L30(F) is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requirements. The core has a 3-stage pipeline and has 32 general-purpose regi...

8
Compact, efficient 64-bit RISC-V processor with 5-stage pipeline
The H50X is an entry level, compact, efficient 64-bit embedded RISC-V processor aimed at embedded systems requiring a large address space. The core has a 5-stage pipeline and is offered in two version...

9
NOEL-V Processor
The NOEL-V is a synthesizable VHDL model of a 64-bit processor that implements the RISC-V architecture. The processor is the first released model in Cobham Gaisler s RiSC-V line of processors that complement the LEON line of processors.

10
Powerful 64-bit embedded RISC-V processor
The Bk7 is a powerful 64-bit embedded RISC-V processor aimed at systems running Linux.

11
RISC-V SOC Platform
A SOC development platform for RISC-V based designs

12
Single issue, embedded RISC-V core with 4-stage pipeline
The Western Digital SweRV Core™ EL2 is a single issue, RV32IMC, single-issue core with a 4-stage in-order pipeline. Like the EH1 and EH2, it supports optional instruction and data closely coupled memo...

13
SweRV EH1 Support Package
The SweRV EH1 Support package (SSP) contains everything needed to deploy a Western Digital SweRV EH1 core in an integrated circuit

14
32-bit Embedded RISC-V Functional Safety Processor
The EMSA5-FS is a processor core designed for functional safety. The fault-tolerant processor uses dual or triple instances of the EMSA5, an efficient 32-bit embedded processor IP core implementing th...

15
AHB-Lite PLIC - RISC-V Compliant Platform Level Interrupt Controller
Fully Parameterized & Programmable Platform Level Interrupt Controller (PLIC) for RISC-V based Processor Systems supporting a user-defined number of interrupt sources and targets, and featuring a single AHB-Lite Slave interface

16
APS1V - Compact Implementation of the RISC-V RV32IMC ISA
Cortus have applied their many years of processor design expertise to the RISC-V ISA. Concentrating on the needs of the embedded designer and leveraging the success of their APS family of processors. ...

17
APS3V - Compact Implementation of the RISC-V RV32IMC ISA
Cortus have applied their many years of processor design expertise to the RISC-V ISA. Concentrating on the needs of the embedded designer and leveraging the success of their APS family of processors. ...

18
APS5V - Compact Implementation of the RISC-V RV32IMAC ISA
Cortus have applied their many years of processor design expertise to the RISC-V ISA. Concentrating on the needs of the embedded designer and leveraging the success of their APS family of processors. ...

19
Digital and mixed-signal IP and ASIC RISC-V reference design for USB Type-C/PD power adapter/charger

IQonIC Works USB-C/PD power adapter IP includes components required to build an integrated programmable power supply (PPS) charger solution.

The USB Type-C source controller detects connectio...

20
FPS29V - Dual Issue Implementation of the RISC-V RV32IMAFC ISA
Cortus have applied their many years of processor design expertise to the RISC-V ISA. Concentrating on the needs of the embedded designer and leveraging the success of their APS family of processors. ...

21
FPS69V - Dual Issue Implementation of the RISC-V RV64GC ISA
Cortus have applied their many years of processor design expertise to the RISC-V ISA. Concentrating on the needs of the embedded designer and leveraging the success of their APS family of processors. ...

22
icyflex-V Low-power 32-bit RISC-V processor
The icyflex-V 32-bit processor core is based on the RV32IMC open-instruction set architecture (ISA) defined by the RISC-V foundation and, as such, is supported by standard state-of-the-art development tools (both open-source and proprietary).

23
Low Power RISCV CPU
SkyeChip

24
Low-Power Deeply Embedded RISC-V Processor
The BA53 is a configurable, low-power, deeply-embedded RISC-V processor IP core.

25
NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
Truechip's NoC Silicon IP provides chip designers and architects with an efficient way to connect multiple TileLink based master and slave devices with reduced latency, power, and area. NoC Silicon IP...

26
RISC-V Platform-Level Interrupt Controller (PLIC) IP
IQonIC Works RISC-V PLIC IP is a platform-level interrupt controller conforming to the RISC-V PLIC specification, for use in systems with a large number of interrupt sources and multiple processor targets for interrupt delivery.

27
RISC-V Timer IP
IQonIC Works RISC-V Timer IP comprises a suite of timers, each conforming to the RISC-V standard machine timer specification.

28
RV12 - RISC-V Processor
A highly configurable single-issue, single-core RV32I, RV64I compliant RISC CPU intended for the embedded market. The RV12 implements a Harvard architecture for simultaneous instruction and data memory accesses.

29
RV32EC_P2 Processor Core IP
IQonIC Works RV32EC_P2 Core is a 2-stage pipeline RISC-V processor core, designed to meet the needs of small, low-power embedded applications, running only trusted firmware.

30
RV32IC_P5 Processor Core IP
IQonIC Works RV32IC_P5 Core is a larger, 5-stage pipeline core RISC-V processor, designed to meet the needs of medium-scale embedded applications that require higher performance, cache memories, and running a mix of trusted firmware and user application code.

31
Ultra-low-power RISC-V based GPU Processor
NEOX™ is a parallel multicore and multithreaded GPU architecture based on the RISC-V RV64C ISA instruction set with adaptive NoC. The number of cores varies from 4 to 64 organized in 1-16 cluster elem...

32
32-bit 8-stage superscalar processor that supports RISC-V specification, including GCN
The 32-bit N45 is an 8-stage superscalar processor that supports RISC-V specification, including (IMAFD) standard instructions, 16-bit compression instructions, and for user-level interrupts. It iss...

33
32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP (DSP)
The 32-bit D45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, “P” Packed-SIMD/DSP instructi...

34
32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux
The 32-bit A45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, “P” Packed-SIMD/DSP instructi...

35
32-bit RISC CPU for low power aplications
The 32-bit RISC CPU core features a 32x16 bit MAC capable of single cycle MAC operations, which enhances execution times of DSP instructions that are critical to DSP applications. The 32 bit datapath has been designed to minimize data, branch and structural hazard-related stalls. It can operate in five operating modes and has a shadow register bank, that provides fast context switching for high priority interrupts.

36
64-Bit 8-stage superscalar processor that supports RISC-V specification, including GCN
The 64-bit NX45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, and “N” for user-level inter...

37
64-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux
The 64-bit AX45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, “P” Packed-SIMD/DSP instruct...

38
64-bit CPU with Modern RISC Architecture, MemBoost and PMA
The 64-bit AX27 is a 5-stage processor that supports the latest RISC-V specification, including G (IMAFD) standard instructions, C 16-bit compression instructions, P Packed-SIMD/DSP instructions, N fo...

39
64-bit CPU with RISC-V Vector Extension
The 64-bit NX27V is a vector processor with 5-stage scalar pipeline that supports the latest RISC-V specification, including the IMAFD standard instructions, "C" 16-bit compression instructi...

40
AndeSight IDE
AndeSight™ has Standard, MCU, RDS and Lite versions and is an Eclipse-based integrated development environment that provides an efficient way to develop embedded applications of the target systems on AndesCore™ based SoC platforms.

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