|
Overview
The DHDLC IP core is used for controlling HDLC/SDLC transmission frame, designed to be used with 8-bit MCU, like DP8051/DP80390. It allows to save MCU time wasted for handling HDLC/SDLC features like bit stuffing, address recognition or CRC computation. The DHDLC has implemented FIFO buffer, for both, receiver and transmitter.
Please sign in to view full IP description :
Tech Specs
Part Number | DHDLC |
Short Description | HDLC/SDLC controller |
Provider |