Flexible video deserializer capable of receiving 18bit, 24bit, and 30bit video data with embedded sync and control carried over four or five serial LVDS compliant inputs. Deserialized data is output on 7-bit parallel busses to the core. A multi-phase PLL with phase selectors on each input channel realigns the local high-speed clock to ensure robust data capture and compatibility with diverse cable assemblies in noisy mixed signal SoC environments.