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You are here : Analog & Mixed Signal > PLL > Clock Generator PLL

TSMC CLN20SOC 20nm Clock Generator PLL - 700MHz-3500MHz

Overview

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock input, a 1-4096 divider in the internal feedback path, and a 1-8 divider at the output. The outputs are 50% duty cycle for all output divider values.

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Tech Specs

Part Number	TCI-TN20SOC-CGHPLL
Short Description	TSMC CLN20SOC 20nm Clock Generator PLL - 700MHz-3500MHz
Provider
Foundry	TSMC
Geometry nm	20
Target Process Node	TSMC CLN20SOC