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Overview
The Digital Blocks DB-I2C-MS-Hs-Mode Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus or Avalon / Qsys Bus to an I2C Bus in Hs-Mode (3.4 Mbit/s) / Fast-Mode Plus (1 Mbit/s) / Fast-Mode (400 Kbit/s) / Standard-Mode (100 Kbit/s). The DB-I2C-MS-Hs-Mode Controller IP Core can also interface a set of Registers within an ASIC / ASSP / FPGA device as well as interface Memory (e.g. SDRAM / SRAM / FLASH) to an I2C Bus
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Tech Specs
| Part Number | DB-I2C-MS-Hs-Mode |
| Short Description | Hs-Mode I2C Controller - 3.4 Mbps, Master / Slave w/FIFO |
| Provider | |
| Maturity | Successful in Customer Implementations |
| Foundry | Chartered, SMIC, LSI, IBM, STMicroelectronics, Silterra, UMC, OKI |
| Target Process Node | Chartered, IBM, LSI. OKI, Silterra, SMIC, STMicroelectronics, Tower, TMSC, UMC |