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Overview
MIPI M-PHY Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A M-PHY configuration (LINK) consists of a minimum of two unidirectional lanes along with associated lane management logic. Each of the M-PHY lanes consists of a lane module (M-TX) that communicates to a corresponding module (M-RX) on the other chip via a serial interconnect that consists of two differential lines. The differential lines can carry both High-Speed (HS) and Low-Speed (LS) signals.
Arasan’s M-PHY’s are of Type 1, which apply to UFS, LLI and CSI-3 protocols. The M-PHY consists of analog transceivers, high speed PLL, data recovery units as well as the state-machine control — all in a single GDSII. The interface to the link protocol-specific controller (host or device) is compliant to the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.
Arasan’s M-PHY’s are of Type 1, which apply to UFS, LLI and CSI-3 protocols. The M-PHY consists of analog transceivers, high speed PLL, data recovery units as well as the state-machine control — all in a single GDSII. The interface to the link protocol-specific controller (host or device) is compliant to the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.
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Tech Specs
Part Number | ARASAN-AIP-MPHY-40LP |
Short Description | MIPI M-PHY - TSMC 40nm |
Provider | |
Maturity | Silicon Proven |
Foundry | TSMC |
Geometry nm | 40 |
Target Process Node | TSMC 40LP |