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Overview
The first IP for PCIe 3.1 with L1 sub-states support
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Tech Specs
| Part Number | 10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC |
| Short Description | 10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC |
| Provider | |
| Maturity | Silicon proven |
| Foundry | TSMC |
| Geometry nm | 5, 7, 12, 16, 22 |
| Target Process Node | TSMC 5nm, 7nm, 12nm, 16nm, 22nm |