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Overview
The Digital Blocks DB-I2C-S-APB / DB-I2C-S-AHB / DB-I2C-S-AXI / DB-I2C-S-AVLN Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC,NIOS II or other high performance microprocessor via the AMBA APB or AHB or AXI-Lite or Altera Avalon System Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more master / slave or slave devices.
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Tech Specs
Part Number | DB-I2C-S-APB / DB-I2C-S-AHB / DB-I2C-S-AXI-Lite |
Short Description | I2C Slave Controller w/FIFO (APB or AHB or AHB-Lite or AXI-Lite Bus) |
Provider | |
Maturity | Successful in Customer Implementations |
Foundry | Chartered, SMIC, LSI, IBM, STMicroelectronics, Silterra, UMC, OKI |
Target Process Node | Chartered, IBM, LSI. OKI, Silterra, SMIC, STMicroelectronics, Tower, TMSC, UMC |