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Overview
The Digital Blocks DB-DMAC-MC-AHB Verilog RTL IP Core is a Multi-Channel DMA Controller supporting 1 – 16 independent data transfers. The Direct Memory Access (DMA) Controller IP Core contains 1 - 16 DMA Controller Engines (i.e. DMA Channels), with a unified AHB5 Master Read/Write interconnects. The DB-DMAC-MC-AHB excels at high data throughput on both small and large data sets. Standard IP releases of number of DMA Controller Engines are 1, 2, 4, 8, and 16.
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Tech Specs
Part Number | DB-DMAC-MC-AHB |
Short Description | AHB Multi-Channel DMA Controller |
Provider | |
Maturity | Successful in Customer Implementations |
Foundry | Chartered, SMIC, LSI, IBM, STMicroelectronics, Silterra, UMC, OKI |
Target Process Node | Chartered, IBM, LSI. OKI, Silterra, SMIC, STMicroelectronics, Tower, TMSC, UMC |