This is a wide-band Analog-to-Digital Converter based on 16 Time-Interleaved Pipeline sub-ADC followed by a digital correction algorithm for gain, offset and skew correction. The differential input is terminated by a 100 Ohms resistor (100 Ohms differential) and followed by an input buffer driving the sub-ADC. The signal amplitude is 1Vpp differential. The analog source driving the ADC shall be ac-coupled to the input pins with two external capacitors of 1nF minimum. The input common-mode is generated internally. The input clock is a differential signal with amplitude of 800mVpp differential.