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Overview
Inicore's iniHDLC family of High-Level Data Link Controller (HDLC) cores consist of a Receiver (FPR: From Primary Rate) and a Transmitter (TPR: To Primary Rate) unit. These single channel HDLC controllers handle all interframe flags, delimiting flags and Frame Check Sequence (FCS) pattern. The FCS is calculated using a CRC-16 polynomial.
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Tech Specs
Part Number | iniHDLC |
Short Description | Single Channel HDLC Controller |
Provider | |
Maturity | Proven in ASIC and FPGA Technologies |
Target Process Node | Technology independent |