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Overview
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the clock reference by an integer between 1 and 4. It provides three 50% duty cycle skew aligned outputs that are divided down from the internal VCO frequency by 1, 2, and 4.
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Tech Specs
Part Number | TCI-TN7FFLVT-DSLPLL |
Short Description | TSMC CLN7FFLVT 7nm Deskew PLL - 300MHz-1500MHz |
Provider | |
Foundry | TSMC |
Geometry nm | 7 |
Target Process Node | TSMC CLN7FFLVT |