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Overview
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divider in the internal feedback path, and a 1-16 divider at the output. The outputs are 50% duty cycle for all output divider values. It delivers optimal jitter performance over all multiplication settings and is suitable for system clock, DDR and general purpose applications where small size, low power and low cost are important.
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Tech Specs
Part Number | TCI-TN7FF-GPMPLL |
Short Description | TSMC CLN7FF 7nm General Purpose PLL - 400MHz-2000MHz |
Provider | |
Foundry | TSMC |
Geometry nm | 7 |
Target Process Node | TSMC CLN7FF |