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You are here : Interface Controller & PHY > AMBA AHB / APB/ AXI > AMBA AXI

DMA AXI4-Stream Interface to AXI Memory Map Address Space

Overview

Digital Blocks DB-AXI4-STREAM-TO-AXI4-MM-BRIDGE Verilog RTL IP Core accepts AXI4-Stream data and control input, converts the control TID to a AXI4 Memory Map address, and signals a DMA Controller to read the data by way of a AXI4 Slave Memory Map read channel.

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Tech Specs

Part Number	DB-AXI4-STREAM-TO-AXI4-MM-BRIDGE
Short Description	DMA AXI4-Stream Interface to AXI Memory Map Address Space
Provider
Maturity	Successful in Customer Implementations
Foundry	SMIC, TSMC, AMS, UMC, Samsung, POWERCHIP, TowerJazz
Target Process Node	TSMC, GlobalFoundaries, UMC, Samsung, SMIC, Intel, Tower Jazz, Powerchip