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You are here : Interface Controller & PHY > AMBA AHB / APB/ AXI > AMBA AXI

AXI4 Memory Map to AXI4-Stream Bridge

Overview

Digital Blocks DB-AXI4-MM-TO-AXI4-STREAM-BRIDGE Verilog RTL IP Core accepts AXI4 Memory Map address, control, and data input, converts the address to an AXI4-Stream TID, and sends the data with TID out on the AXI4-Stream Interface.

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Tech Specs

Part Number	DB-AXI4-MM-TO-AXI4-STREAM-BRIDGE
Short Description	AXI4 Memory Map to AXI4-Stream Bridge
Provider
Maturity	Successful in Customer Implementations
Foundry	SMIC, TSMC, AMS, UMC, Samsung, POWERCHIP, TowerJazz
Target Process Node	TSMC, GlobalFoundaries, UMC, Samsung, SMIC, Intel, Tower Jazz, Powerchip