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PCI Express GEN 4/5 Port SERDES PHY - Samsung 8LPP

Overview

Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY for PCIe 5.0 operates at 2.5Gbps, 5Gbps, 8Gbps, 16Gbps and 32Gbps, and is designed to meet higher performance standards required for enterprise market applications. The PHY additionally features an interface capability that allows integration with other customer-designed serial protocol PCS layers at any baud rate up to 16Gbps. The PMA is delivered as a hard macro while the fully-synthesizable soft PCS includes performing all necessary calibration and self-test functions. The universal PHY architecture allows forming arbitrarily wide efficient links by being independent of the need for a common CMU.

Tech Specs

Part NumberPCI Express GEN 4/5 Port SERDES PHY - Samsung 8LPP
Short DescriptionPCI Express GEN 4/5 Port SERDES PHY - Samsung 8LPP
Provider
Maturity In Design
FoundryAMS, Samsung
Geometry nm8
Target Process NodeSamsung 8nm LPP
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