|
Overview
The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs needing additional performance. This AHB Multi-matrix system contains a flexible Power Management Unit for controlling power sequencing of the CPU and peripherals. The PMU can easily be extended to control additional cores, peripherals and even analog subsystems on the same SOC.
Additionally, the subsystem includes two DMA controllers for easily moving data from user peripherals to internal SRAM.
Additionally, the subsystem includes two DMA controllers for easily moving data from user peripherals to internal SRAM.
Please sign in to view full IP description :
Tech Specs
Part Number | AHB Performance Subsystem - ARM M0 |
Short Description | AHB Performance Subsystem - ARM M0 |
Provider | |
Maturity | Silicon Proven |
Target Process Node | all |