USB 3.1 PHY (10G/5G) in Samsung (14nm, 11nm, 10nm, 8nm, SF5, SF5A, SF4E)

Overview

The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offering consists of Host, Device, and Dual-Role Device controllers, PHYs with and without support for the USB Type-C™ connectivity specification and DisplayPort 1.3 support, verification IP, IP Prototyping Kits, and IP software development kits. These elements enable quick development of advanced chip designs incorporating the 10 Gbps SuperSpeed USB standard. The Synopsys USB 3.1 IP is targeted for integration into SoCs for media storage, creation, and playback devices, requiring faster bandwidth between PCs and portable electronic devices. Optimized for low power, the Synopsys USB 3.1 Controller and PHY IP allow designers to maximize power efficiency for extended battery life. The Synopsys USB 3.1 IP enables the fastest SuperSpeed USB data transfer speeds while lowering overall power consumption. As the leading supplier of USB IP, Synopsys provides designers with a high-performance, low-power, and area-efficient IP solution, for cost-effective integration into system-on-chip designs. Synopsys’ expertise in developing and supporting USB enables us to build a low risk, high quality SuperSpeed USB IP solution.

Tech Specs

Part Numberdwc_usb31sspphy_samsung
Short DescriptionUSB 3.1 PHY (10G/5G) in Samsung (14nm, 11nm, 10nm, 8nm, SF5, SF5A, SF4E)
Provider
Maturity Available on request
FoundryAMS, Samsung
Geometry nm4, 5, 8, 10, 11, 14
Target Process NodeSamsung 14nm, 11nm, 10nm, 8nm, SF5, SF5A, SF4E - LPP, LPE
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