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Overview
The multi-lane Synopsys Multi-Protocol 25G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY is small in area and provides a low active and standby power solution that supports multiple electrical standards, including PCI Express (PCIe) 4.0, 25G and 400G Ethernet, Cache Coherent Interconnect for Accelerators (CCIX), SATA, and other industry-standard interconnect protocols. Using leading-edge design, analysis, simulation, and measurement techniques, the multi-protocol 25G PHY delivers signal integrity and jitter performance that exceeds the standards’ electrical specifications.
The configurable transmitter and receiver equalizers along with Continuous Calibration and Adaptation (CCA) enable designers to control and optimize signal integrity and performance across voltage and temperature variations.
The configurable transmitter and receiver equalizers along with Continuous Calibration and Adaptation (CCA) enable designers to control and optimize signal integrity and performance across voltage and temperature variations.
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Tech Specs
Part Number | dwc_25g_phy_tsmc |
Short Description | 25G PHY in TSMC (16nm, 12nm, N7, N6) |
Provider | |
Maturity | Available on request |
Foundry | TSMC |
Geometry nm | 6, 7, 12, 16 |
Target Process Node | TSMC 16nm, 12nm, N7, N6 - FFC, FF |