|
Overview
This Display Port v1.4 Rx PHY IP Core supports Channel capacity, offering programmable analog characteristics like CDR Bandwidth, Equalizer Strength, Terminator Resistor, and BGR Voltage, up to 5.4 Gbps per channel (HBR2). It also includes testability options such as PLL alone test and analog signal monitor, ensuring comprehensive functionality for signal processing and testing in digital display systems.
Please sign in to view full IP description :
Tech Specs
Part Number | DisplayPort v1.4 Rx PHY IP in 40LP |
Short Description | Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 40LP |
Provider | |
Maturity | In Production |
Foundry | TSMC |
Geometry nm | 40 |
Target Process Node | TSMC 40LP |