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Overview
The eSi-HP-FP-Fused-Multiply-Add IP core implements half-precision (16-bit), IEEE 754 compliant, floating-point fused multiply and add operations.
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Tech Specs
| Part Number | eSi-HP-FP-Fused-Multiply-Add |
| Short Description | Half precision, IEEE 754, floating point fused multiply add |
| Provider | |
| Maturity | Silicon proven in multiple products |