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PCIe 4/5 Refenece Clock PLL with SSCS - GLOBALFOUNDRIES 12LP+

Overview

Analog Bits’ Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS). The integrated PHY for PCIe 4.0 operates at 2.5Gbps, 5Gbps, 8Gbps and 16Gbps, and is designed to meet higher performance standards required for enterprise market applications. The PHY additionally features an interface capability that allows integration with other customer-designed serial protocol PCS layers at any baud rate up to 16Gbps. The PMA is delivered as a hard macro while the fully-synthesizable soft PCS includes performing all necessary calibration and self-test functions. The universal PHY architecture allows forming arbitrarily wide efficient links by being independent of the need for a common CMU.

Tech Specs

Part NumberPCIe Gen3/4/5 LC Class SSCG PLL - GF 12LP
Short DescriptionPCIe 4/5 Refenece Clock PLL with SSCS - GLOBALFOUNDRIES 12LP+
Provider
FoundryGlobalFoundries
Geometry nm12
Target Process NodeGLOBALFOUNDRIES 12nm LP+
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