Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 serial bus standard where SRIS (Separate RefClk Independent Spread-Spectrum clock generation) is required. This SSCG PLL is designed for digital logic processes and use robust design techniques to work in noisy SoC environments. The SSCG PLL macro is implemented in Analog Bits’ proprietary architecture that uses core and 1.8V IO devices. Eliminating band-gaps and integrating all on-chip components such as capacitors helps the jitter performance significantly and reduces stand-by power.