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Overview
Analog Bits’ PCIe Gen3 SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen3 serial bus standard where SRIS (Separate RefClk Independent Spread-Spectrum clock generation) is required. This SSCG PLL is designed for digital logic processes and use robust design techniques to work in noisy SoC environments.
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Tech Specs
| Part Number | PCIe Gen2/33 Class SSCG PLL - GF 12LP |
| Short Description | PCIe3 SSCG PLL - GLOBALFOUNDRIES 12LP+ |
| Provider | |
| Foundry | GlobalFoundries |
| Geometry nm | 12 |
| Target Process Node | GLOBALFOUNDRIES 12nm LP+ |