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Overview
Analog Bits’ PCIe Gen 5 Ref Clock SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express Gen4 and Gen5 serial bus standard where SRIS (Separate RefClk Independent Spread-spectrum clock generation) is required. This SSCG PLL is designed for digital logic processes and uses robust design techniques to work in noisy SoC environments.
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Tech Specs
Part Number | PCIe Gen4/5 Ref Clock Generator |
Short Description | PCIe5 Ref Clock SSCG PLL - TSMC 6FF |
Provider | |
Foundry | TSMC |
Geometry nm | 6 |
Target Process Node | TSMC 6nm CLN6FF |