The combined PHY complies with the PIPE, Serial ATA, PCIe, USB, USB 3.0, USB 2.0, and PCIe Peripheral Component Interconnect Express interface protocols (USB High-speed and Full speed). Supporting additional internal power gating, reference clock control, and PLL control allows for reduced power use. The PHY is also particularly advantageous for a range of situations under varied considerations of power consumption because of the adaptability of the previously described low power mode option.