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Overview
The Analog-Frontend (AFE) IP consists of programmable current and voltage preamplifier followed by a Successive Approximation Register (SAR) architecture ADC using charge-redistribution technique. The ADC IP is configurable regarding resolution (6-13 bit) and sample rate (up to 10kS/s). The preamplifier offers programmable gain from 0.5 to 4. The input voltage range is quasi-rail-to-rail guaranteeing more than +- 1.7 V @ 1.8 V power supply. An optional calibration technique can be applied to compensate degraded mismatch behavior of t echnology capacitors. The overall power consumption of the AFE IP sums up with 10.5 μW at 1 kHz input signal.
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Tech Specs
Part Number | AFE13b010kS180nm |
Short Description | Ultra-Low Power 6 - 13 Bit 0.5 -10 kS/s 10μW Analog Front End |
Provider | |
Maturity | silicon evaluated |
Foundry | XFAB |
Geometry nm | 18 |
Target Process Node | XFAB XT018 |