The WDT-APB core implements 32-bit count down counter with a programmable timeout interval and logic to generate an interrupt and a reset signal on its timeout. The main purpose of the Watchdog IP Core is to trigger a system reset in case of software failure to prevent a system lock-up.
Via a 32-bit APB interface, the host processor can choose the timeout interval, enable, disable or clear the interrupt and reset lines, and pause or resume the timer. If the counter is enabled, it will decrement on every clock cycle. When the counter reaches zero, the interrupt output is asserted and the counter is reloaded with the timeout value. In case that the interrupt is not cleared before the counter reaches the zero value again, the output reset signal is asserted.