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Overview
The AXI4-SGDMA IP core implements a Host-to-Peripheral (H2P), or a Peripheral-to-Host (P2H) Direct Memory Access (DMA) engine, which interfaces the host system with an AXI4 Memory-Mapped master port and the peripheral with either a slave or a master AXI4-Stream port.
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Tech Specs
| Part Number | AXI4-SGDMA |
| Short Description | AXI4 to/from AXI4-Stream Scatter-Gather DMA |
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