The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general-purpose accelerators, memory expanders, and smart I/O devices requiting high performance, heterogeneous computing for data-intensive workloads.
The Synopsys CXL 2.0 Integrity and Data Encryption (IDE) Security IP Module provides confidentiality, integrity and replay protection for FLITs in the case of CXL.cache and CXL.mem protocols and for Transaction Layer Packets (TLP) in the case of CXL.io. The Security Module is compliant with the IDE specification as defined for CXL 2.0 which also references PCI Express IDE specification