Our efficient Core performs serial‐to‐parallel conversion on data received from a IR Receiver Diode. The processor can read a complete status of the DIRDA at any time during the functional operation. The DIRDA includes a programmable internal prescaler which is able to divide a timing reference clock input by divisors of 1 to 128 and produce clock for driving internal receiver logic. We also equipped our core with processor‐interrupt system. Interrupts can be programmed in accordance to your requirements, minimizing computing required to handle the communications link. It can be provided with the small 8‐bit SRAM like interface and APB slave interface. In MODE0 DIRDA decode whole IR frame, detect transmission errors and key release. In MODE1, internal FIFO is activated allowing 32 symbols to be stored during signal receive. Interrupt trigger level register may be set any value from 1 to 32 symbols. All gathered makes it an ideal choice for very popular IR protocols implementations like NEC, SIRC, TC9012 data format or other non‐standard IR protocols.