This PHY IP supports both USB 3.1 Gen1 & Gen2. By providing a full on-chip physical transceiver solution with Electro Static Discharge (ESD) protection, an integrated self-test module with built-in jitter injection. This USB 3.1 Gen2 PHY IP implements USB3.1 Gen2 transceiver and can be used as host and device. PHY IP supports USB3.1 Gen2 high speed data rate up to 10Gbps with integrated mixed signal circuit, also supports Gen1 5Gbps data rate.