12.5G Multiprotocol Serdes IP, Silicon Proven in TSMC 28HPC+

Overview

The multi-protocol SerDes PHY consists of Serial ATA (SATA) conforming with SATA 3.0 Specification, Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification with support for PIPE interface spec, Universal Serial Bus (USB) compliant with USB 3.0, USB 2.0 (USB Highspeed and Full speed), and USB 3.0 compliant with USB 3.0. Support for extra PLL control, reference clock control, and inbuilt power gating control results in lower power usage. Additionally, the PHY is broadly usable for diverse circumstances under varying considerations of power consumption because the aforementioned low power mode option is customizable.

Tech Specs

Part Number12.5G Multiprotocol Serdes IP in 28HPCP
Short Description12.5G Multiprotocol Serdes IP, Silicon Proven in TSMC 28HPC+
Provider
Maturity In Production
FoundryTSMC
Geometry nm28
Target Process NodeTSMC 28HPC+
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