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Overview
The Digital Blocks DB-DMAC-MC-AXI4-MM-STREAM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces.
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Tech Specs
Part Number | DB-DMAC-MC-AXI4-MM-STREAM |
Short Description | Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers |
Provider | |
Maturity | Successful in Customer Implementations |