IGAAFEV04A is a 500 MHz analog front-end circuit. IGAAFEV04A contains four 12 bit 250 MHz SAR 2-channel ADCs, four 12 bit 500 MHz Current Steering 3-channel DACs and one 500 MHz General-Purpose PLL. IGAAFEV04A support I2C, JTAG, and APB 3-in-1 interface to handle configuration and functionality control for ADC, DAC, and PLL. Individual power-down mode of each ADC, DAC, and PLL is built in for power consumption reduction.
IGAAFEV04A is designed and fabricated in TSMC 12 nm FF CMOS process.