The USB 2.0 PHY IP Core is a full physical layer (PHY) IP solution created for excellent performance and low power consumption. The High-Speed USB 2.0 transceiver for usage with hosts, devices, or OTG function controllers is implemented by the USB2.0 IP. The UTMI+ level 3 specification is followed by the USB2.0 PHY IP, which supports both Full-Speed (12 Mbps) and Low-Speed (1.5 Mbps) data rates. 480Mbps of high-speed data flow are provided by combining mixed-signal circuits. The USB2.0 PHY IP transceiver was designed to have a small chip size and low power consumption without sacrificing performance or data throughput with full on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, a clock generating block provided by an internal PLL, and a resistor termination calibration circuit.