12.5G Multiprotocol Serdes IP, Silicon Proven in UMC 28HPC

Overview

The multi-protocol SerDes PHY consists of Serial ATA (SATA) conforming with SATA 3.0 Specification, Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification with support for PIPE interface spec, Universal Serial Bus (USB) compliant with USB 3.0, USB 2.0 (USB Highspeed and Full speed), and USB 3.0 compliant with USB 3.0. Due to the provision of extra PLL control, reference clock control, and integrated power gating control, lower power consumption is obtained.
Additionally, because the aforementioned low power mode option is customizable, the PHY is extensively useful for a variety of situations with diverse power consumption considerations.

Tech Specs

Part Number12.5G Multiprotocol Serdes IP in 28HPC
Short Description12.5G Multiprotocol Serdes IP, Silicon Proven in UMC 28HPC
Provider
Maturity In Production
FoundryUMC
I understand
This website uses cookies to store information on your computer/device. By continuing to use our site, you consent to our cookies. Please see our Privacy Policy to learn more about how we use cookies and how to change your settings if you do not want cookies on your computer/device.