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Overview
RapidIO is a high performance, low pin count, packet switched, full duplex, system level interconnect architecture. The architecture addresses the need for faster bus speeds in an intra-system interconnect for microprocessors, digital signal processors and communications. RapidIO interconnect architecture is partitioned into a layered hierarchy of specifications which includes Logical, Common Transport and Physical layers, in which the Physical layer defines the interface between two devices and the packet transport mechanism, flow control and electrical characteristics.
KNiulink RapidIO PHY offers the physical layer specification solution as defined in the RapidIO Specification Rev 4.0/3.1/2.2. The IP supports four-lane running at different transmission speeds up to 6.25/ 10.3125/25.78125Gbps.
KNiulink RapidIO PHY offers the physical layer specification solution as defined in the RapidIO Specification Rev 4.0/3.1/2.2. The IP supports four-lane running at different transmission speeds up to 6.25/ 10.3125/25.78125Gbps.
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Tech Specs
Part Number | KNiulink RapidIO PHY |
Short Description | RapidIO PHY |
Provider | |
Maturity | Silicon Proven |
Foundry | SMIC, TSMC, UMC |
Geometry nm | 12, 14, 16, 22, 28, 40, 65 |
Target Process Node | SMIC 12 SFe,SMIC 14 SF+, TSMC 12 FFC, TSMC 16 FFC, TSMC 22 ULP, TSMC 28 HPC+, TSMC 40G, TSMC 65G, UMC 28 HPC+ |