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You are here : Interface Controller & PHY > AMBA AHB / APB/ AXI > AMBA AXI

DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List

Overview

The Digital Blocks DB-DMAC-MC2-DL-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces.

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Tech Specs

Part Number	DB-DMAC-MC2-DL-MM2S-S2MM
Short Description	DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List
Provider
Maturity	Successful in Customer Implementations