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Overview
Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high performance computing applications. The area-efficient PHY provides a low active and standby power solution that supports multiple electrical standards, including PCI Express® (PCIe®) 6.0, 1G to 112Gbps electrical PHY for 400G/800G Ethernet, Cache Coherent Interconnect for Accelerators (CCIX), Compute Express Link (CXL), JESD204C, CPRI, SATA, and other industry-standard interconnect protocols. Using leading-edge design, analysis, simulation, and measurement techniques, the multi-protocol 112G PHY delivers signal integrity and jitter performance that exceeds the standards electrical specifications.
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Tech Specs
Part Number | dwc_112g_lrm_phy_tsmc5ff_x2ns |
Short Description | 112G LR-Max Ethernet PHY for TSMC N5 |
Provider | |
Foundry | TSMC |
Geometry nm | 5 |
Target Process Node | TSMC 5FF |